1. Field of the Invention
The present invention relates to a semiconductor device including a field-effect transistor, and a method of manufacturing the device.
2. Description of the Related Art
An integrated circuit has been highly integrated, and accordingly an MOS field-effect transistor (FET) which is a constituting element has been increasingly miniaturized. When the miniaturization of the MOSFET is advanced following a scaling rule, a gate insulating film becomes very thin, the withstand voltage degrades between a source/drain region and a gate electrode in an edge portion of a gate electrode to which a high electric field is applied during operation, and a leakage current is generated. To handle this problem, in Jpn. Pat. Appln. KOKAI Publication No. 4-137562, a plurality of insulating films having different permittivities are disposed between a gate electrode and a semiconductor substrate, the permittivity of the insulating film on a gate electrode side is raised, and the film is extended to the side face of the gate electrode. In Jpn. Pat. Appln. KOKAI Publication No. 8-264777, a technique has been disclosed in which the gate electrode is surrounded with a material having a comparatively high permittivity, and accordingly an electric field is reduced even in the gate insulating film or gate side wall in the vicinity of the gate electrode, especially in opposite end portions of the gate insulating film.
On the other hand, a tri-gate type field-effect transistor has been developed in which a fin-like (plate-like) semiconductor region is disposed on a substrate, and gate electrodes are disposed on three faces of a middle portion via gate insulating films. In this tri-gate type field-effect transistor, the gate electrodes exist on the opposite side faces and upper faces of the semiconductor region in which a channel is formed. This constitution enhances controllability of the gate electrode with respect to the potential of the channel region as compared with a field-effect transistor having a usual structure. As a result, a short channel effect is inhibited, an element is miniaturized, and an element operation can be speeded up. However, in a structure of a region in which the channel is formed and which has an edge (arris), there is a phenomenon in which a strong electric field is generated in the edge portion, causing degradation in reliability. This is an obstacle to realization of high-speed operation of the element.
To reduce the electric field in the gate insulating film, for example, it is supposed that the gate insulating film be formed to be thick. However, when the gate insulating film is formed to be thick, capacitive coupling between the channel region and the gate electrode is weakened. As a result, controllability of the gate electrode with respect to the potential of the channel region is lowered, the short channel effect is enhanced, and degradation of a current driving capability of the element is caused.
Thus, there exists a field-effect transistor of such a type that the semiconductor region in which the channel is formed is brought into contact with the gate insulating film via a plurality of faces, and the edge exists in boundaries among the faces as in the tri-gate type field-effect transistor. In this field-effect transistor, the above-described tradeoff lies between the enhancement of controllability of the gate electrode and the enhancement of the reliability, and this has been an obstacle to speeding-up the operation of the element.
Therefore, there has been a demand for realization of a high-performance semiconductor device capable of relaxing a strong electric field in a gate insulating film in the vicinity of an edge of a semiconductor region in which a channel region is formed to enhance reliability of an element and enable operation at a sufficiently high speed.